专利名称：INSULATING GATE TYPE LOGIC CIRCUIT 发明人：SAKAGAMI KENJI
nodeselector申请号：JP22729186
申请日：19860926
公开号：JPS6382514A
公开日：
19880413
专利内容由知识产权出版社提供
摘要：PURPOSE:To prevent the generation of a through current at the time of a stand by providing a circuit with respective logical gates connected to the respective output nodes of plural transfer gates and controlling the logical gate to be turned off at the time of the stand by. CONSTITUTION:In a barrel shifter in which input data I0-I7 is shifted based on shift control signals SH1, SH2 and outputted as output data O0-O7, a CMOS inverter IA, an IB selector array part SA of an input and an output sides are disposed and the pre- and post-stage transfer ,TB of the array part SA are constituted of N channel MOS transistors. Further, a selector output is earthed through an N channel MOS , the is gate controlled by a signal obtained by inverting an enable signal by a CMOS inverter IE1 and when the enable signal goes to O, the transistor TN is turned on to bring the SN to an earth potential.
申请人：TOSHIBA CORP,TOSHIBA MICRO COMPUT ENG CORP
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