DM9161A
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
1                                                                                                                                                                                                                                                                                    Final
Version: DM9161A-DS-F01
October 16, 2009
DM9161A
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
Final
Version: DM9161A-DS-F01
October 16, 2009
DM9161A
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
Final                                                                                                                                                                                                                                                                      2
Version: DM9161A-DS-F01 October 16, 2009
Table of Contents
1. General Description (3)
2. Features (3)
3. Block Diagram (4)
4. Pin Configuration: (5)
5. 6 5.1 Normal MII Interface, 21 pins ..................................................6 5.2 Media Interface, 8 5.3 LED Interface, 8 5.4 Mode, 8 5.5 Bias and Clock, 9 5.6 Power, 9 5.7 Table A (Media Type Selection)..............................................9 5.8 Pin Maps of Normal MII, Reduced MII, and 10Base-T GPSI
(7-Wired) Mode (10)
6. 11 6.1 LED Functional Description.. (12)
7. 13 7.1 13 7.2 .15 7.2.1 15 7.2.1.1 .16 7.2.1.16 7.2.1.3 Parallel to 16 7.2.1.4 NRZ to 16 7.2.1.5 16 7.2.1.6 16 7.2.1.7 4B5B 17 7.2.2 18 7.2.2.1 18 7.2.2.2 18 7.2.2.3 MLT-3 to
..............18 7.2.2.4 Clock .18 7.2.2.5 NRZI 18 7.2.2.6 Serial 18 7.2.2.18 7.2.2.8 Code 18 7.2.2.9 .18 7.2.3 18 7.2.4 19 7.2.5 19 7.2..19 7.2.7 MII 20 7.2.8 Serial Management Interface (20)
7.2.9 Management Interface – Read Frame
<20 7.2.10 Management Interface – Write 20 7.2.11 Power 21 7.2.12 Power 21 7.2.13 Reduced Transmit 21 7.2.14 Feedback Vout and Vin 21 7.3  H
P Auto-MDIX Functional  Description.. (22)
8. MII Register Description (23)
8.1 Basic Mode Control Register (BMCR) - 00............................24 8.2 Basic Mode Status Register (BMSR) - 01.............................25 8.3 PHY ID Identifier Register #1 (PHYIDR1) - 02......................26 8.4 PHY ID Identifier Register #2 (PHYIDR2) - 03......................26 8.5 Auto-negotiation Advertisement Register (ANAR)
- 04......................................................................................27 8.6 Auto-negotiation Link Partner Ability Register (ANLPAR) - 0528 8.7 Auto-negotiation Expansion Register (ANER)
- 06......................................................................................29 8.8 DAVICOM Specified Configuration Register (DSCR) –16.....29 8.9 DAVICOM Specified Configuration and Status Register
(DSCSR) - 17......................................................................31 8.10 10Base-T Configuration / Status (10BTCSR) - 18...............32 8.11 DAVICOM Specified Interrupt Register - 21........................32 8.12 DAVICOM Specified Receive Error Counter Register (RECR) -
<33 8.13 DAVICOM Specified Disconnect Co
unter Register (DISCR) -
<33 8.14 DAVICOM Hardware Reset Latch State
Register (RLSR) - 24 (34)
9. DC and AC Electrical Characteristics
9.1 Absolute Maximum Ratings ( 25°C )........................................35 9.2 35 9.3 DC 36 9.4 AC Electrical Characteristics & Timing
<36 9.4.1 .36 9.4.2 Oscillator/36 9.4.3 MDC/37 9.4.4 MDIO Timing when OUTPUT 37 9.4.5 MDIO Timing when OUTPUT .37 9.4.6 100Base-TX Transmit 38 9.4.7 100Base-TX Transmit Timing Diagra
<.38 9.4.8 100Base-TX Receive 38 9.4.9 MII 100Base-TX Receive Timing Diagram. (39)
9.4.10 MII 10Base-T Nibble Transmit Timing Parameters ..........39 9.4.11 MII 10Base-T Nibble Transmit Timing
Diagram (39)
9.4.12 MII 10Base-T Receive Nibble Timing Parameters ..........40 9.4.13  MII 10Base-T Receive Nibble Timing
Diagram (40)
9.4.14 Auto-negotiation and Fast Link Pulse Timing Parameters40 9.4.15 Auto-negotiation and Fast Link Pulse Timing Diagram ....41 9.4.16 RMII Receive 41 9.4.17 RMII Transmit 41 9.4.18 RMII Timing Diagram.. (42)
9.4.19 RMII Timing Parameter (42)
9.4.20 Magnetics Selection Guide (43)
10. Package Information (44)
11.Order Information (45)
DM9161A
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
3                                                                                                                                                                                                                                                                                    Final
Version: DM9161A-DS-F01
October 16, 2009
1. General Description
The DM9161A is a physical layer, single-chip, and low power transceiver for 100BASE-TX and 10BASE-T operations. On the media side, it provides a direct interface either to Unshielded Twisted Pair Category 5 Cable (UTP5) for 100BASE-TX Fast Ethernet, or UTP5/UTP3 Cable for 10BASE-T Ethernet. Through the Media Independent Interface (MII), the DM9161A connects to the Medium Access Control (MAC) layer, ensuring a high inter operability from different vendors.
TheDM9161A uses a low power and high performance advanced CMOS process. It contains the entire physical layer functions of 100BASE-TX as defined by IEEE802.3u, including the Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA), Twisted Pair Physical Medium Dependent Sublayer (TP-PMD), 10BASE-TX Encoder/Decoder (ENC/DEC), and Twisted Pair Media Access Unit (TPMAU). The DM9161A provides a strong support for the auto-negotiation function, utilizing automatic media speed and protocol selection. Furthermore, due to the built-in wave shaping filter, the DM9161A needs no external filter to transport signals to the media in 100BASE-TX or 10BASE-T Ethernet operation.
2. Features
negotiation autoFully comply with IEEE 802.3 / IEEE 802.3u 10Base-T/ 100Base-TX, ANSI X3T12 TP-PMD 1995 standard  Support MDI/MDI-X auto crossover function (Auto-MDI)
Support Auto-Negotiation function, compliant with IEEE 802.3u
Fully integrated Physical layer transceiver On-chip filtering with direct interface to magnetic  transformer  Selectable repeater or node mode
Selectable MII or RMII (Reduced MII) mode for
100Base-TX and 10Base-TX.  Selectable  MII or GPSI (7-Wired) mode for 10Base-T
Selectable full-duplex or half-duplex operation    MII management interface with maskable interrupt output capability
Provide Loopback mode for easy system diagnostics
LED status outputs indicate Link/ Activity, Speed10/100
and Full-duplex/Collision. Support Dual-LED optional control
Single low power Supply of 3.3V with an advanced
CMOS technology
Very Low Power consumption modes:
● Power Reduced mode (cable detection) ● Power Down mode
● Selectable TX drivers for 1:1 or 1.25:1 transformers for additional power reduction. 1: 1 transformers only when HP Auto-MDIX Enable .
Compatible with 3.3V and 5.0V tolerant I/Os  48-pin LQFP
DM9161A
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
Final                                                                                                                                                                                                                                                                      4
Version: DM9161A-DS-F01 October 16, 2009
3. Block Diagram
DM9161A
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
5                                                                                                                                                                                                                                                                                    Final
Version: DM9161A-DS-F01
October 16, 2009
4. Pin Configuration:
1
2
3
4
5
6
7
8
9
10
11
12
373839404142434445464748
A V D D R
A V D D T R X +
T X -
R X -
A G N D
A G N D
T X +
A V D D R
P W R D W N
L E D 0/O P 0
L E D 1/O P 1
RXDV/TESTMODE RXER/RXD[4]/RPTR
DISMDIX DVDD RESET#XT2XT1DGND NC AGND BGRESG BGRES
13
14151617181920
21222324TXD[1]LED2/OP2
CABLESTS/LINKSTS DGND
TXER/TXD[4]TXD[3]TXD[2]TXEN TXCLK/ISOLATE DVDD
TXD[0]MDC 35
36
34
33
32
31
30
29
28
27
26
25M D I O
R X D [0]/P H Y A D [0]
R X D [2]/P H Y A D [2]R X D [3]/P H Y A D [3]R X D [1]/P H Y A D [1]
D V D D
L E D M O D E
M D I N T R #
R X C L K /10B T S E R
D G N D
C R S /P H Y A
D [4]
C O L /R M I I
DM9161A

版权声明：本站内容均来自互联网，仅供演示用，请勿用于商业和其他非法用途。如果侵犯了您的权益请与我们联系QQ:729038198，我们将在24小时内删除。