REALTEK SINGLE CHIP
OCTAL 10/100 MBPS FAST ETHERNET TRANSCEIVER
RTL8208
1. Features (2)
2. General Description (2)
3. Block Diagram (3)
4. Pin Assignments (4)
5. Pin Description (6)
5.1 Media Connection Pins (6)
5.2 Power and Ground Pins (6)
5.3 Miscellaneous Pins (7)
5.4 RMII/SMII/SS-SMII Pins (8)
5.5 SMI (Serial Management Interface) Pins (9)
5.6 LED Pins (9)
5.7 Mode Control Pins (10)
5.8 Reserved Pins (11)
6. Register Descriptions (12)
6.1 Register 0: Control (12)
6.2 Register1: Status (14)
6.3 Register2: PHY Identifier 1 Register (15)
6.4 Register3: PHY Identifier 2 Register (15)
6.5 Register4: Auto-Negotiation Advertisement (16)
6.6 Register5: Auto-Negotiation Link Partner Ability (17)
6.7 Register6: Auto-Negotiation Expansion (18)
7. Functional Description (19)
7.1 General (19)
7.1.1 SMI (Serial Management Interface) (19)
7.1.2 Port Pair Loop Back Mode (PP-LPBK) (19)
7.1.3 PHY Address (20)
7.1.4 Auto-Negotiation (20)
7.1.5 Full-Duplex Flow Control (20)
7.2 Initialization and Setup (20)
7.2.1 Reset (20)
7.2.2 Setup and configuration (20)
7.3 10Base-T (20)
7.3.1 Transmit Function (20)
7.3.2 Receive Function (21)
7.3.3 Link Monitor (21)
7.3.4 Jabber (21)
7.3.5 Loopback (21)
7.4 100Base-TX (21)
7.4.1 Transmit Function (21)
7.4.2 Receive Function (21)
7.4.3 Link Monitor (22)
7.4.4 Baseline Wander Compensation (23)
7.5 100Base-FX (23)
7.5.1 Transmit Function (23)
7.5.2 Receive Function (23)
7.5.3 Link Monitor (24)
7.5.4 Far-End-Fault-Indication (FEFI) (24)
7.6 RMII/SMII/SS-SMII (24)
7.6.1 RMII (Reduced MII) (25)
7.6.2 SMII (Serial MII) (25)
7.5.3 SS-SMII (Source Synchronous -Serial MII) (27)
7.7 Power Saving and Power Down Mode (28)
7.7.1 Power Saving Mode (28)
7.7.2 Power Down Mode (28)
7.8 LED Configuration (28)
7.8.1 LED Blinking Time (28)
7.8.2 Serial Stream Order (29)
7.8.3 Bi-Color LED (30)
7.9  2.5V Power Generation (31)
8. Design and Layout Guide (32)
8.1 General Guidelines (32)
8.2 Differential Signal Layout Guidelines (32)
8.3 Clock Circuit (32)
8.4 2.5V power (32)
8.5 Power Planes (32)
8.6 Ground Planes (32)
8.7 Transformer Options (32)
9. Application information (33)
9.1 10Base-T/100Base-TX Application (33)
9.2 100Base-FX Application (34)
10. Electrical Characteristics (35)
10.1 Absolute Maximum Ratings (35)
10.2 Operating Range (35)
10.3 DC Characteristics (35)
10.4 AC Characteristics (36)
10.5 Digital Timing Characteristics (37)
10.6 Thermal Data (38)
11. Mechanical Dimensions (39)
1. Features
Supports 8-port integrated physical layer and
transceiver for 10Base-T and 100Base-TX
Up to 8 ports support of 100Base-FX
Reduced 100Base-FX interface  (patented)
Robust baseline wander correction for improved 100BASE-TX performance
Fully compliant with IEEE 802.3/802.3u
IEEE 802.3u compliant Auto-negotiation for 10/100 Mbps control
Hardware controlled  Flow control advertisement ability  Supports RMII/SMII/SS-SMII interfaces
Multiple driving capabilities of RMII/SMII/SS-SMII  Supports 25MHz crystal as clock source for RMII with 50MHz REFCLK output for MAC  Very low power consumption
Supports port-pair loop mode (PP-LPBK mode)        Supports two Power reduction methods:
1. Power saving mode (cable detection)
2. Power down mode
Power-on auto reset function eliminates the need for external reset circuits
Flexible LED display modes through 2-wire serial  LED control interface
128-pin PQFP
2.5V/
3.3V power supply
0.25µm, CMOS technology
2. General Description
The RTL8208 is a highly integrated 8 port, 10Base-T/100Base-TX/FX, Ethernet transceiver implemented in 0.25µm CMOS technology. It is currently the world’s smallest Octal-PHY chip package with many special patented features. Traditional SD pins in 100Base-FX are omitted by Realtek patent to obtain fewer pin-count. Flexible hardware settings are provided to configure the various operating modes of the chip. The RTL8208 consists of 8 separate and independent channels. Each channel consists of  an RMII/SMII/SS-SMII interface to MAC controller, and hardware pins are used to configure the interface for RMII, or SMII, or SS-SMII mode. In RMII mode, another hardware pin is used to set port-pair loop mode (PP-LPBK mode), which can extend physical transmission length or perform physical media transport operations without any switch controller. In addition, the RTL8208 features very low power consumption, as low as 1.8 W (max.). Additionally, pin-outs are designed to provide optimized  direct routing can be implemented, which simplifies the layout work and reduces EMI noise issues.
3. Block Diagram
4. Pin Assignments
MDC MDIO VSS TX_EN[0]TXD0[0]TXD1[0]CRS_DV[0]RXD0[0]RXD1[0]VSS X1
TXON[0]TXOP[0]VSSA RXIP[0]RXIN[0]VDDAL IBREF VDDAH VCTRL X2VDDAH
TXOP[1]
TXON[1]VDDAH VDD
V S S
V D D
V D D
R X D 1[3]
T X _S Y N C
V S S
R X D 0[3]
R X _S Y N C
T X D 1[3]
C R S _
D V [3]
T X D 0[3]
T X _E N [3]
T X _E N [1]
T X D 0[1]
R X D 1[2]
T X D 0[2]
R X D 0[2]
T X D 1[2]
T X _E N [2]
C R S _
D V [2]
R X D 0[1]
R X D 1[1]
C R S _
D V [1]
T X D 1[1]
T X _E N [4]
T X D 0[4]
C R S _
D V [5]
V D D
T X D 1[5]
T X _E N [5]
V S S
T X D 0[5]
R X D 0[4]
R X D 1[4]
C R S _
D V [4]
T X D 1[4]
R X D 0[5]
R X D 1[5]
V S S A
V D D A H
T X O N [2]
T X O P [2]
V S S A
R X I P [2]
R X I N [2]
V D D A L
V D D A L
R X I N [1]
R X I P [1]
V D D A H
V S S A
R X I P [4]
R X I N [4]
V D D A L
V D D A L
R X I N [3]
R X I P [3]
V S S A
T X O P [3]
T X O N [3]
T X O P [4]
V D D A L
V D D A L
R X I N [5]
R X I P [5]
V S S A
T X O P [5]
T X O N [5]
V D D A H
V D D A H
T X O N [4]
R X I N [6]
T X O N [6]
T X O P [6]
V S S A
R X I P [6]
VDD
TXD0[7]
RXD1[6]
TX_EN[7]
VSS
RXD0[6]
TXD1[6]
CRS_DV[6]
TXD0[6]
TX_EN[6]
TXD1[7]
CRS_DV[7]
RESET#
REFCLK
LED_CLK LED_DATA
RXD1[7]
RXD0[7]
VSSA
RXIP[7]
VDDAL RXIN[7]
VDDAH
VDDAH
TXOP[7]
TXON[7]
RTL8208 'I' stands for input; 'O' stands for output; 'A' stands for analog; ‘D’ stands for digital
Pin Name  Pin# Type  Pin Name  Pin# Type
VSSA
RXIP[1]
RXIN[1]
VDDAL
VDDAL
RXIN[2]
RXIP[2]
VSSA
TXOP[2]
TXON[2]
VDDAH
VDDAH
TXON[3]
TXOP[3]
VSSA
RXIP[3]
RXIN[3]
VDDAL
VDDAL
RXIN[4]
RXIP[4]
VSSA
TXOP[4]
TXON[4]
VDDAH
VDDAH
TXON[5]
TXOP[5]
VSSA
RXIP[5]
RXIN[5]
VDDAL
VDDAL
RXIN[6]
RXIP[6]
VSSA
TXOP[6]
TXON[6]
VDDAH
VDDAH
negotiation auto
TXON[7]
TXOP[7]
VSSA
RXIP[7]
RXIN[7]
VDDAL
RESET#
REFCLK
LED_DATA/LEDMODE[1] LED_CLK/LEDMODE[0] RXD1[7]
RXD0[7]/DRIVE[0]
CRS_DV[7]/MODE[0] TXD1[7]
TXD0[7]
TX_EN[7]
VDD
VSS
RXD1[6]/DISBLINK RXD0[6]/DRIVE[1]
CRS_DV[6]/MODE[1] TXD1[6]
TXD0[6]
TX_EN[6] 1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
AGND
AI
AI
A VDD
A VDD
AI
AI
AGND
AO
AO
A VDD
A VDD
AO
AO
AGND
AI
AI
A VDD
A VDD
AI
AI
AGND
AO
AO
A VDD
A VDD
AO
AO
AGND
AI
AI
A VDD
A VDD
AI
AI
AGND
AO
AO
A VDD
A VDD
AO
AO
AGND
AI
AI
A VDD
I
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
DVDD
DGND
I/O
I/O
I/O
I
I
I
RXD1[5]/LED_BLNK_TIME
RXD0[5]
CRS_DV[5]/TP_PAUSE
TXD1[5]
TXD0[5]
TX_EN[5]
VDD
VSS
RXD1[4]/PHY_ADDR[4]
RXD0[4]
CRS_DV[4]/RX_CLK
TXD1[4]
TXD0[4]
TX_EN[4]/TX_CLK
VDD
SYNC/TX_SYNC
RX_SYNC/RPT_MODE
VSS
RXD1[3]/PHY_ADDR[3]
RXD0[3]
CRS_DV[3]/FX_PAUSE
TXD1[3]
TXD0[3]
TX_EN[3]
VDD
VSS
RXD1[2]/TEST
RXD0[2]
CRS_DV[2]/FX_DUPLEX
TXD1[2]
TXD0[2]
TX_EN[2]
RXD1[1]
RXD0[1]
CRS_DV[1]/SEL_TXFX[1]
TXD1[1]
TXD0[1]
TX_EN[1]
VDD
VSS
RXD1[0]
RXD0[0]
CRS_DV[0]/SEL_TXFX[0]
TXD1[0]
TXD0[0]
TX_EN[0]
VSS
MDIO
MDC
X1
X2
VCTRL
VDDAH
IBREF
VDDAL
RXIN[0]
RXIP[0]
VSSA
TXOP[0]
TXON[0]
VDDAH
VDDAH
TXON[1]
TXOP[1]
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
I/O
O
I/O
I
I
I
DVDD
DGND
I/O
O
O
I
I
I
DVDD
I
I
DGND
I/O
O
I/O
I
I
I
DVDD
DGND
I/O
O
I/O
I
I
I
O
O
I/O
I
I
I
DVDD
DGND
O
O
I/O
I
I
I
DGND
I/O
I
I
O
I/O
A VDD
AO
A VDD
AI
AI
AGND
AO
AO
A VDD
A VDD
AO
AO

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