DM9161
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
Final
1
Version: DM9161-DS-F02May 10,2002
1. General Description
The DM9161 is a physical layer, single-chip, and low power transceiver for 100BASE-TX and 10BASE-T operations. On the media side, it provides a direct interface either to Unshielded Twisted Pair Category 5Cable (UTP5) for 100BASE-TX Fast Ethernet, or UTP5/UTP3 Cable for 10BASE-T Ethernet. Through the Media Independent Interface (MII), the DM9161connects to the Medium Access Control (MAC) layer,ensuring a high inter operability from different vendors.The DM9161 uses a low power and high performance CMOS process. It contains the entire physical layer
functions of 100BASE-TX as defined by IEEE802.3u,including the Physical Coding Sublayer (PCS),Physical Medium Attachment (PMA), Twisted Pair Physical Medium Dependent Sublayer (TP-PMD),10BASE-TX Encoder/Decoder (ENC/DEC), and Twisted Pair Media Access Unit (TPMAU). The DM9161 provides a strong support for the auto-negotiation function, utilizing automatic media speed and protocol selection. Furthermore, due to the built-in wave shaping filter, the DM9161 needs no external filter to transport signals to the media in 100BASE-TX or 10BASE-T Ethernet operation.
2. Block Diagram
MII
Management Control
Biasing/Power Block
Clock Circuit Block 100Base-TX Transceiver
LED Driver
MII Interface
MII Register
100Base-TX
PCS
10Base-T TX/RX Module
Auto-Negotiation
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DM9161
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
2
Final
Version: DM9161-DS-F02
May 10,2002
Table of Contents
1. 3
2. Block Diagram ......................................................3
3. 4
4. Pin Configuration: 5
5. 65.1 Normal MII Interface, .65.2 Media Interface, 85.3 LED Interface, 85.4 Mode, 2 pins .......................................................85.5 Bias and Clock, 95.6 Power, 95.7 95.8 Pin Maps of Normal MII, Reduced MII, and
10Base-T GPSI (7-Wired) 106. 117. 127.1 127.2 .147.2.1 147.2.1.1 157.2.1.2 Scrambler ...................................................157.2.1.3 Pa
rallel to 157.2.1.4 NRZ to 157.2.1.5 157.2.1.6 157.2.1.7 4B5B 167.2.2 177.2.2.1 177.2.2.2 177.2.2.3 MLT-3 to NRZI Decoder .............................177.2.2.4 Clock .187.2.2.5 NRZI 187.2.2.6 Serial 187.2.2.7 Descrambler ...............................................187.2.2.8 Code 187.2.2.9 187.2.3 10Base-T Operation ......................................187.2.4 187.2.5 187.2..187.2.7 MII 197.2.8 Serial 197.2.9 Management Interface – Read Frame
<197.2.10 Management Interface – Write Frame
<197.2.11 Power 207.2.12 Power 207.2.13 Reduced Tra
nsmit 208. MII 218.1 Basic Mode Control Register (BMCR) - 00.......228.2 Basic Mode Status Register (BMSR) - 01........238.3 PHY ID Identifier Register #1 (PHYIDR1) - 02..248.4 PHY ID Identifier Register #2 (PHYIDR2) - 03..248.5 Auto-negotiation Advertisement Register (ANAR)
- 04...................................................................258.6 Auto-negotiation Link Partner Ability Register
(ANLPAR) - 05.................................................268.7 Auto-negotiation Expansion Register (ANER)
- 06...................................................................278.8 DAVICOM Specified Configuration Register
(DSCR) –16.......................................................278.9 DAVICOM Specified Configuration and Status
Register (DSCSR) - 17.....................................298.10 10Base-T Configuration / Status (10BTCSR) - 18
.........................................................................308.11 DAVICOM Specified Interrupt Register - 21...308.12 DAVICOM Specified Receive Error Counter
Register (RECR) - 22.......................................318.13 DAVICOM Specified Disconnect Counter
Register (DISCR) - 23......................................318.14 DAVICOM Hardware Reset Latch State
Register (RLSR) - 24.......................................319. DC and AC Electrical Characteristics
9.1 Absolute Maximum Ratings ( 25°C )...................329.2 329.3 DC 339.4 AC Electrical Characteristics & Timing
<.339.4.1 .339.4.2 Oscillator/339.4.3 MDC/MDIO Timing ........................................349.4.4 MDIO Timing when OUTPUT 349.4.5 MDIO Timing when OUTPUT 349.4.6 100Base-TX Transmit 359.4.7 100Base-TX Transmit .359.4.8 100Base-TX Receive 359.4.9 MII 100Base-TX Receive Timing Diagram. (36)
DM9161
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
Final                                                                                                                                                                                                                                                                        3Version: DM9161-DS-F02
May 10,2002
9.4.10 MII 10Base-T Nibble Transmit Timing
Parameters (36)
9.4.11 MII 10Base-T Nibble Transmit Timing
Diagram (36)
9.4.12 MII 10Base-T Receive Nibble Timing
Parameters (37)
9.4.13 MII 10Base-T Receive Nibble Timing
Diagram (37)
9.4.14 Auto-negotiation and Fast Link Pulse Timing
Parameters (37)
9.4.15 Auto-negotiation and Fast Link Pulse Timing
Diagram (38)
9.4.16 RMII Receive 389.4.17 RMII Transmit 389.4.18 RMII Timing Diagram.. (39)
9.4.19 RMII 3910. 4010.1 Network Interface 4010.2 10Base-T/4010.3 10Base-T (Power Reduction Application).......4110.4 Power 4210.5 Ground 4310.6 Power 4410.7 Magnetics 4510.8 Crystal 4511. 4612.Order Information.. (47)
DM9161
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
4
Final
Version: DM9161-DS-F02
May 10,2002
3. Features
Fully complies with IEEE 802.3u 10Base-T/100Base-TX
Comply with ANSI X3T12 TP-PMD 1995 standard  Support Auto-Negotiation function, compliant with IEEE 802.3u
Fully integrated Physical layer single chip with direct interface to magnetic
Integrated 10Base-T and 100Base-TX transceiver  On-chip filtering, no need for external filters  Selectable repeater or node mode
Selectable MII or RMII (Reduced MII) interface.
Selectable GPSI (7-Wired) or MII mode at the 10Base-T.
Selectable full-duplex or half-duplex operation
MII management interface with maskable interrupt
output capability
Provide Loopback mode for easy system diagnostics
LED status outputs indicate Link/ Activity, Speed10/100and Full-duplex/Collision.
Single low power Supply of 3.3V with 0.35µm CMOS technology
Very Low Power consumption modes:● Power Reduced mode (cable detection)● Power Down mode
● Selectable TX drivers for 1:1 or 1.25:1 transformers for additional power reduction.
negotiation autoCompatible with 3.3V and 5.0V tolerant I/Os
48-pin LQFP small package (1x1 cm)
DM9161
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
Final                                                                                                                                                           
                                                                                                            5Version: DM9161-DS-F02
May 10,2002
4. Pin Configuration: DM9161 LQFP
A V D D
A V D D
R X +
T X -
R X -
A G N D
A G N D
T X +
A V D D
P W R D W N
F D X /C O L L E D #/O P 0
S P E E D L E D #/O P 1
RXDV/TESTMODE RXER/RXD[4]/RPTR
DVDD DVDD RESET#XT2XT1DGND NC AGND BGRESG BGRES
TXD[1]LINK/ACTLED#/OP2
CABLESTS/LINKSTS DGND
TXER/TXD[4]TXD[3]TXD[2]TXEN TXCLK/ISOLATE DVDD
TXD[0]MDC M D I O
R X D [0]/P H Y A D [0]
R X D [2]/P H Y A D [2]R X D [3]/P H Y A D [3]R X D [1]/P H Y A D [1]
D V D D
R X E N
M D I N T R #
R X C L K /S C R A M E N /10B T S E R
D G N D
C R S /P H Y A
D [4]
C O L /R M I I

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