Device Description
The N25Q is the first high-performance multiple input/output serial Flash memory de-
vice manufactured on 65nm NOR technology. It features execute-in-place (XIP) func-
tionality, advanced write protection mechanisms, and a high-speed SPI-compatible bus
interface. The innovative, high-performance, dual and quad input/output instructions
enable double or quadruple the transfer bandwidth for READ and PROGRAM opera-
tions.
Features
The memory is organized as 256 (64KB) main sectors that are further divided into 16
subsectors each (4096 subsectors in total). The memory can be erased one 4KB subsec-
tor at a time, 64KB sectors at a time, or as a whole.
The memory can be write protected by software through volatile and nonvolatile pro-
tection features, depending on the application needs. The protection granularity is of
64KB (sector granularity) for volatile protections
The device has 64 one-time programmable (OTP) bytes that can be read and program-
med with the READ OTP and PROGRAM OTP commands. These 64 bytes can also be
permanently locked with a PROGRAM OTP command.
The device also has the ability to pause and resume PROGRAM and ERASE cycles by us-
ing dedicated PROGRAM/ERASE SUSPEND and RESUME instructions.
Operating Protocols
The memory can be operated with three different protocols:
•Extended SPI (standard SPI protocol upgraded with dual and quad operations)
•Dual I/O SPI
•Quad I/O SPI
The standard SPI protocol is extended and enhanced by dual and quad operations. In
addition, the dual SPI and quad SPI protocols improve the data access time and
throughput of a single I/O device by transmitting commands, addresses, and data
across two or four data lines.
XIP Mode
XIP mode requires only an address (no instruction) to output data, improving random
access time and eliminating the need to shadow code onto RAM for fast execution.
All protocols support XIP operation. For flexibility, multiple XIP entry and exit methods
are available. For applications that must enter XIP mode immediately after powering
up, XIP mode can be set as the default mode through the nonvolatile configuration reg-
ister bits.
include中文
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以深圳市美光存储技术有限公司提供的参数为例，以下为N25Q128A13EF840F的详细参数，仅供参
考
Table 15: Flag Status Register Bit Definitions (Continued)
Notes:  1.Register bits are read by READ FLAG STATUS REGISTER command. All bits are volatile.
2.These program/erase controller settings apply only to PROGRAM or ERASE command cy-
cles in progress, or to the specific WRITE command cycles in progress as shown here.
3.Status bits are reset automatically.
4.Error bits must be reset by CLEAR FLAG STATUS REGISTER command.
5.Typical errors include operation failures and protection errors caused by issuing a com-
mand before the error bit has been reset to 0.
Command Definitions
Table 16: Command Set
128Mb, 3V , Multiple I/O Serial Flash Memory
Command Definitions

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