PCI Express 3.0 Testing Approaches for PHY and Protocol Layers
name title
Agenda
•
Introduction to PCI Express 3.0
– Trends and Challenges
•
Physical Layer Testing Overview
– – – Transmitter Design & Validation Transmitter Compliance Receiver & Summary of Tools for PCIe PHY Testing
•
Protocol
– – – • Planning probe access Time to confidence Information density Applications
•
Summary
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2010-4-26
Tektronix Innovation Forum 2010
PCI Express 3.0 Technology Timeline
Today 2009
0.5 Release 0.7 Release 0.71 Release
2010
2011
2112
Base Spec
0.5 Release 0.7 Draft
CEM Spec
0.3 Release
Test Spec
Deployment Phase Integration Phase
– – Product Development PCI-SIG Tool Development
Silicon Phase
–
CEM Spec Development
Presentation Content based on .9 Base Specification Draft and .7 CEM Specification Draft
Tektronix Involved in PCIe EWG, CEM, and Serial Enabling Working Groups
3 2010-4-26 Tektronix Innovation Forum 2010
PCI Express 3.0
Trends and Implications
Industry/Technology Trends
• Data transfer rates continue to increase:
2.5
5
8 GT/s
• 128b/130b encoding • Backwards interoperability • Energy efficiency (Lower mW/Gb/s)
Implications
• Greater system complexity increases
the engineering challenge
• Higher data rate signals have less
margin – requires de-embedding
• Crosstalk, skew, noise and attenuation
more significant
• Link training and power management
continue to be the most difficult challenges
4 2010-4-26 Tektronix Innovation Forum 2010
High Speed Serial Test Challenges
Design Verification Compliance Test
Transaction Layer
System Integration
validation verificationDigital Validation & Debug
Data Link Analysis
Digital validation & Debug
Data Link Layer
Logical Sub-block
Complete Validation, Debug, Compliance Solutions!! Receiver Test Simulation Signal Integrity
Eye and Jitter Analysis Characterization & Validation Direct Synthesis
Compliance Testing
Physical Layer
+ -
Electrical Sub-block
Serial Data Network & Link Analysis
Tx
+ + -
path
+ -
Rx
5
2010-4-26
Tektronix Innovation Forum 2010

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