易语言字符串转数组SJ005-1
CHANGZHOU  INSTITUTE  OF  TECHNOLOGY
毕 业 设 计 说 明 书
题目： 基于电流源的高速数模转换器设计                           
二级学院：  电子信息与光电工程学院                               
专    业： 电子科学与技术           
班级：12电子二   
学生姓名： 胡文艳           
学号：12020810     
指导教师： 韩益锋           
职称：讲师         
评阅教师：             
职称：             
  2016 年 4月
摘要
随着计算机技术、信号处理技术、微电子技术的快速发展，先进的电子系统不断涌现，所以对干芯片中数字部分与模拟部分接口电路的研究显得尤为重要。特别是在无线通信等领域，需要用到高速的数模转换器。典型的如数据信号依据某种机制被一调制到载波上，和载波一起在有线或无线的通道中传输;当接收器接收到信号时，可根据对于应用性和可行性的不同选择在数字或模拟领域中解调。在高速数据转换电路中，速度、精度、功耗和芯片面积是四个关键的性能指标。任何设计都要根据具体的要求在这四个方面进行折中。
本文主要介绍了高采样速率的电流型数模转换器的设计和仿真。本文设计的数模转换器采用“6+2+2”的分割结构——高6位和中间2位采用相互独立的温度计编码，低2位采用二进制编码。在数字部分设计了Latch，3-8译码器及选通电路等模块，模拟部分设计了偏置电路及电流源阵列等模块。在仿真过程中，发现glitch一直是一个很难解决的问题。本文设计的数模转换器主要是采用了分段编码的形式，并且使用了带有源极负反馈的电流开关，从而减小毛刺（glitch）。另外，电流源采用共源共栅的结构提高了转换精度。
关键词  DAC；分段译码；温度计编码；二进制编码；锁存器；毛刺(glitch)。
Abstract
With the fast development of computer technology, digital processing technology and microelectronic technology, all kinds of advanced electronic systems interfaces important are presented continually. Consequently the research on the between the digital and analog domains is becoming more and more than ever. Especially in the wireless high-speed DACs (Digital-to-Analog converters) are communication area, implicated per vigorous requirement. As a typical example, the data such as signal is modulated onto a carrier according to some scheme. The signal is subsequently sent over the wire or wireless channel for the transportation together with the carrier. When receiving, the receiver will demodulate and extract the data. The modulation can be done in either way of the digital and analog domain on the dependent of application and feasibility purpose. In high-speed data conversion circuit , the speed , precision, power consumption and chip area are four key performance indicators . Any design must be based on the specific requir
ements of these four areas compromise .
This paper describes a high sampling rate of the current type DAC design and simulation. This design uses DAC "6 +2 +2" split structure - high six and intermediate two separate thermometer coding using low two binary encoding. In the digital part of the design of the Latch ,3-8 decoder and gating circuit modules, analog part of the design of the bias circuit and current source array module. During the simulation, the glitch has been found to be a very difficult problem. This design uses a segmented DAC is mainly coded form, and with the use of a negative feedback current source switching, thereby reducing glitch (glitch). In addition, the current source using cascode structure improves conversion accuracy.
Key words DAC; Segmented Architecture; Thermometer decoded; Binary decoded; Latch; Glitch.

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