Orcad 16.5 DRC setting
Design Rules Options tab
 
Use
To
Scope
Select the scope of the design rules check. The scope can cover the entire design, or selected schematic folders and pages.
Mode
Specify to check either instances or occurrences.Capture automatically sets this option based on the project type. All designs default to use instances. If a PCB or Schematic design is complex or has occurrence properties, the default shifts to occurrences. Capture recommends the preferred mode, which you can override.
Action
Specifies either a design rules check, deletion of existing DRC markers or creating DRC markers for warning.
Note: The DRC markers are automatically deleted when you run a subsequent design rules check.
Use the Ignore DRC Warnings option to specify any DRC Warnings that you do not want to be checked during the DRC check and netlisting. For example, to ignore the ALG0051 or ALG0016 warnings during netlist, specify these in the Ignore Warnings dialog.
Design Rules
Select the type of rules to run, electrical and / orphysical.
Report file
Specify the path and file name for the report.
View Output
Open the design rules check report file in a text editor.
Browse
Displays a standard Windows dialog box for selecting files.
Electrical Rules tab
 
Electrical Rules
 
Use
To
Check single node nets
Check if the design contains any nets with only one connection.
Check no driving source and Pin type conflicts
 
Check duplicate net names
Check if the design contains any duplicate net names.
Check off-page connectorconnections
Verify that off-page connector nets on a schematic page match those on other schematic pages.
Check hierarchical portconnections
Verify that hierarchical pins in a hierarchical block match hierarchical ports in the child schematic folder or folders.
Errors are generated if the number of hierarchical ports and hierarchical pins differ between the parent and child schematic folders. Also generates errors if the types of hierarchical ports are not identical between the parent and child schematic folders.
Check unconnected bus nets
Check for and reports all unconnected bus nets. This check will run for all unconnected bus nets across schematics in a design.
Check unconnected pins
Check for any pins on the design that are unconnected or do not have no-connect attached.
ignore subsequent bad blocksCheck SDT compatibility
Check for SDT compatibility. For more information about SDT compatibility, seeSaving in SDT format.
 
Reports
 
Use
To
Report all net names
List the names of all nets in the report file.
Report off-grid objects
List all objects that are on Fine grid in the report file.
Report hierarchical ports and off-page connectors
List all hierarchical ports and off-page connectors in the report file.
Report misleading tapconnections
Checks for and reports those signals that are wrongly connected through a Bus Tap to a bus. Also checks for missing bus taps.
Physical Rules tab
 
Physical Rules
 
Use
To
Check power pin visibility
Check if the visibility property of a power pin on one section of multi-section part is different from the corresponding power pin on another section of the part.
Check missing/illegal PCB Footprint property
Check if the PCB footprint property on a part is missing or the property defined is illegal.
Check Normal Convert view sync
Check if the pin numbers on the normal view of a part are different from the pin numbers on the convert view.
Check incorrect Pin_Groupassignment
Check if all pins in same pin group in a part are of the same type.
Check high speed props syntax
Check the syntax of the high speed properties of the nets in the design.
Check missing pin numbers
Check if any part on the design has missing pin numbers.
Check device with zero pins
Check if any part on the design has no pin on the part.
Check power ground short
Check if the type of power pin name inside a part is connected to a net on the schematic with a different name.
Check Name Prop consistency
Check if the occurrences of a hierarchical block have the same "Name" property.
 
Reports
 
Use
To
Report Visible unconnected power pins
List the names of all visible unconnected power pins.
Report unused part packages
List the names of any unused part packages.
Report invalid packaging
List any invalid packaging.
Report identical part references
List any identical part references.
ERC Matrix tab
 
Use
To
Matrix
Set the rules used by the Design Rules Check when testing connections between pins, hierarchical blocks, and hierarchical ports.
The pins, hierarchical ports, and off-page connectors are listed in columns and rows in the table. A test is represented by the intersection of a row and column. Either the intersection of a row and column is empty, or it contains a "W" or an "E." An empty intersection represents a valid connection, a "W" is a warning, and an "E" represents an error.
You can cycle through these three settings by pointing to an intersection and clicking the mouse button until the desired setting displays. You can also type W for warning, E for error, and N for an empty intersection. In addition to these keys, you can use the arrow keys to select other intersections.
Restore defaults
Restore the ERC matrix to its default values.

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