VER 1.0
Evaluation Board Test Report
FSL106MR Demoboard ver1.0 2nd
March 17, 2010
Contents
1. General Description of FSL106MR (3)
1.1. Features of FSL106MR (3)
1.2. Internal Block Diagram of FSL106MR (3)
2. General Specifications for Evaluation Board (4)
2.1. A photograph of the Evaluation Board (5)
2.2. Printed Circuit Board (5)
2.3. Schematic of the Evaluation Board (7)
2.4. Bill of Materials (8)
2.5. Transformer and Winding Specifications (9)
3. Test Conditions & Items (10)
4. Performance of Evaluation Board (11)
4.1. Start up waveforms (11)
4.2. Normal Operation (12)
4.3. Volatage stress of 2nd diodes and Drain (14)
4.4. Output Ripple & Noise (16)
4.5. Protections (19)
4.6. Output Regulation & Efficiency (26)
4.7. Standby power (27)
4.8. Temperature Measurement (28)
4.9. EMI Measurement (28)
1. General Description of FSL106MR
1.1. Features of FSL106MR
9Internal Avalanche-Rugged SenseFET (650V)
9Under 50mW Standby Power Consumption at 265V AC, No-load Condition with Burst Mode
9Precision Fixed Operating Frequency with Frequency Modulation for Attenuating EMI
9Internal Startup Circuit
9Built-in Soft-Start: 15ms
9Pulse-by-Pulse Current Limiting
9Various Protections: Over-Voltage Protection (OVP), Overload Protection (OLP), Output-Short Protection (OSP), Abnormal Over-Current Protection (AOCP), Internal Thermal Shutdown Function with Hysteresis (TSD)
9Auto-Restart Mode
9Under-Voltage Lockout (UVLO)
9Low Operating Current: 1.5mA
9Adjustable Peak Current Limit
1.2. Internal Block Diagram of FSL106MR
2. General Specifications for Evaluation Board
Table 1. Evaluation Board specifications
Fairchild Device FSL106MR
Input voltage range 90 ~ 265 V AC
Frequency 60Hz
Output full-load condition 1    3.3V / 0.6A, 12V / 0.2A & 20V / 0A Output full-load condition 2    3.3V / 0.6A, 12V / 0A & 20V / 0.2A
2.1. A photograph of the Evaluation Board
- Dimension: 101 × 41 [mm 2spring framework documentation
]
Fig. 1. Photograph of evaluation board (Demoboard ver1.0).
2.2. Printed Circuit Board
(a) Top silk
Top view
(b) Bottom silk
(c) Bottom pattern
Fig. 2. PCB of the evaluation board.

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